//==========================================================================
// Copyright (c) 2000-2008,  Elastos, Inc.  All Rights Reserved.
//==========================================================================
/*
 *  linux/include/asm-arm/arch-pxa/pxa-regs.h
 *
 *  Author: Nicolas Pitre
 *  Created: Jun 15, 2001
 *  Copyright: MontaVista Software Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#ifndef _PXA_REGS_H_
#define _PXA_REGS_H_

#include <bitfield.h>

// FIXME hack so that SA-1111.h will work [cb]

#ifndef __ASSEMBLY__
typedef unsigned short  Word16 ;
typedef unsigned int    Word32 ;
typedef Word32          Word ;
typedef Word            Quad [4] ;
typedef void            *Address ;
typedef void            (*ExcpHndlr) (void) ;
#endif

#if 0
/*
 * PXA Chip selects
 */

#define PXA_CS0_PHYS 0x00000000
#define PXA_CS1_PHYS 0x04000000
#define PXA_CS2_PHYS 0x10000000
#define PXA_CS3_PHYS 0x14000000

#endif

/*
 * PXA SDRAM banks
 */

#define PXA_SDRAM_BANK0 0xa0000000
#define PXA_SDRAM_BANK1 0xa4000000
#define PXA_SDRAM_BANK2 0xa8000000
#define PXA_SDRAM_BANK3 0xac000000

/*
 * UARTs
 */

#define FFUART FFRBR
#define FFRBR  __REG(0x40100000)  /* Receive Buffer Register (read only) */
#define FFTHR  __REG(0x40100000)  /* Transmit Holding Register (write only) */
#define FFIER  __REG(0x40100004)  /* Interrupt Enable Register (read/write) */
#define FFIIR  __REG(0x40100008)  /* Interrupt ID Register (read only) */
#define FFFCR  __REG(0x40100008)  /* FIFO Control Register (write only) */
#define FFLCR  __REG(0x4010000C)  /* Line Control Register (read/write) */
#define FFMCR  __REG(0x40100010)  /* Modem Control Register (read/write) */
#define FFLSR  __REG(0x40100014)  /* Line Status Register (read only) */
#define FFMSR  __REG(0x40100018)  /* Modem Status Register (read only) */
#define FFSPR  __REG(0x4010001C)  /* Scratch Pad Register (read/write) */
#define FFISR  __REG(0x40100020)  /* Infrared Selection Register (read/write) */
#define FFDLL  __REG(0x40100000)  /* Divisor Latch Low Register (DLAB = 1) (read/write) */
#define FFDLH  __REG(0x40100004)  /* Divisor Latch High Register (DLAB = 1) (read/write) */

#define BTUART BTRBR
#define BTRBR  __REG(0x40200000)  /* Receive Buffer Register (read only) */
#define BTTHR  __REG(0x40200000)  /* Transmit Holding Register (write only) */
#define BTIER  __REG(0x40200004)  /* Interrupt Enable Register (read/write) */
#define BTIIR  __REG(0x40200008)  /* Interrupt ID Register (read only) */
#define BTFCR  __REG(0x40200008)  /* FIFO Control Register (write only) */
#define BTLCR  __REG(0x4020000C)  /* Line Control Register (read/write) */
#define BTMCR  __REG(0x40200010)  /* Modem Control Register (read/write) */
#define BTLSR  __REG(0x40200014)  /* Line Status Register (read only) */
#define BTMSR  __REG(0x40200018)  /* Modem Status Register (read only) */
#define BTSPR  __REG(0x4020001C)  /* Scratch Pad Register (read/write) */
#define BTISR  __REG(0x40200020)  /* Infrared Selection Register (read/write) */
#define BTDLL  __REG(0x40200000)  /* Divisor Latch Low Register (DLAB = 1) (read/write) */
#define BTDLH  __REG(0x40200004)  /* Divisor Latch High Register (DLAB = 1) (read/write) */

#define STUART STRBR
#define STRBR  __REG(0x40700000)  /* Receive Buffer Register (read only) */
#define STTHR  __REG(0x40700000)  /* Transmit Holding Register (write only) */
#define STIER  __REG(0x40700004)  /* Interrupt Enable Register (read/write) */
#define STIIR  __REG(0x40700008)  /* Interrupt ID Register (read only) */
#define STFCR  __REG(0x40700008)  /* FIFO Control Register (write only) */
#define STLCR  __REG(0x4070000C)  /* Line Control Register (read/write) */
#define STMCR  __REG(0x40700010)  /* Modem Control Register (read/write) */
#define STLSR  __REG(0x40700014)  /* Line Status Register (read only) */
#define STMSR  __REG(0x40700018)  /* Reserved */
#define STSPR  __REG(0x4070001C)  /* Scratch Pad Register (read/write) */
#define STISR  __REG(0x40700020)  /* Infrared Selection Register (read/write) */
#define STDLL  __REG(0x40700000)  /* Divisor Latch Low Register (DLAB = 1) (read/write) */
#define STDLH  __REG(0x40700004)  /* Divisor Latch High Register (DLAB = 1) (read/write) */

#define IER_DMAE  (1 << 7) /* DMA Requests Enable */
#define IER_UUE   (1 << 6) /* UART Unit Enable */
#define IER_NRZE  (1 << 5) /* NRZ coding Enable */
#define IER_RTIOE (1 << 4) /* Receiver Time Out Interrupt Enable */
#define IER_MIE   (1 << 3) /* Modem Interrupt Enable */
#define IER_RLSE  (1 << 2) /* Receiver Line Status Interrupt Enable */
#define IER_TIE   (1 << 1) /* Transmit Data request Interrupt Enable */
#define IER_RAVIE (1 << 0) /* Receiver Data Available Interrupt Enable */

#define IIR_FIFOES1 (1 << 7) /* FIFO Mode Enable Status */
#define IIR_FIFOES0 (1 << 6) /* FIFO Mode Enable Status */
#define IIR_TOD     (1 << 3) /* Time Out Detected */
#define IIR_IID2    (1 << 2) /* Interrupt Source Encoded */
#define IIR_IID1    (1 << 1) /* Interrupt Source Encoded */
#define IIR_IP      (1 << 0) /* Interrupt Pending (active low) */

#define FCR_ITL2    (1 << 7) /* Interrupt Trigger Level */
#define FCR_ITL1    (1 << 6) /* Interrupt Trigger Level */
#define FCR_RESETTF (1 << 2) /* Reset Transmitter FIFO */
#define FCR_RESETRF (1 << 1) /* Reset Receiver FIFO */
#define FCR_TRFIFOE (1 << 0) /* Transmit and Receive FIFO Enable */
#define FCR_ITL_1   (0)
#define FCR_ITL_8   (FCR_ITL1)
#define FCR_ITL_16  (FCR_ITL2)
#define FCR_ITL_32  (FCR_ITL2|FCR_ITL1)

#define LCR_DLAB  (1 << 7) /* Divisor Latch Access Bit */
#define LCR_SB    (1 << 6) /* Set Break */
#define LCR_STKYP (1 << 5) /* Sticky Parity */
#define LCR_EPS   (1 << 4) /* Even Parity Select */
#define LCR_PEN   (1 << 3) /* Parity Enable */
#define LCR_STB   (1 << 2) /* Stop Bit */
#define LCR_WLS1  (1 << 1) /* Word Length Select */
#define LCR_WLS0  (1 << 0) /* Word Length Select */

#define LSR_FIFOE (1 << 7) /* FIFO Error Status */
#define LSR_TEMT  (1 << 6) /* Transmitter Empty */
#define LSR_TDRQ  (1 << 5) /* Transmit Data Request */
#define LSR_BI    (1 << 4) /* Break Interrupt */
#define LSR_FE    (1 << 3) /* Framing Error */
#define LSR_PE    (1 << 2) /* Parity Error */
#define LSR_OE    (1 << 1) /* Overrun Error */
#define LSR_DR    (1 << 0) /* Data Ready */

#define MCR_LOOP (1 << 4) */
#define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */
#define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */
#define MCR_RTS  (1 << 1) /* Request to Send */
#define MCR_DTR  (1 << 0) /* Data Terminal Ready */

#define MSR_DCD  (1 << 7) /* Data Carrier Detect */
#define MSR_RI   (1 << 6) /* Ring Indicator */
#define MSR_DSR  (1 << 5) /* Data Set Ready */
#define MSR_CTS  (1 << 4) /* Clear To Send */
#define MSR_DDCD (1 << 3) /* Delta Data Carrier Detect */
#define MSR_TERI (1 << 2) /* Trailing Edge Ring Indicator */
#define MSR_DDSR (1 << 1) /* Delta Data Set Ready */
#define MSR_DCTS (1 << 0) /* Delta Clear To Send */

/*
 * I2C registers
 */

#define IBMR  __REG(0x40301680)  /* I2C Bus Monitor Register - IBMR */
#define IDBR  __REG(0x40301688)  /* I2C Data Buffer Register - IDBR */
#define ICR   __REG(0x40301690)  /* I2C Control Register - ICR */
#define ISR   __REG(0x40301698)  /* I2C Status Register - ISR */
#define ISAR  __REG(0x403016A0)  /* I2C Slave Address Register - ISAR */

#define ICR_START   (1 << 0)    /* start bit */
#define ICR_STOP    (1 << 1)    /* stop bit */
#define ICR_ACKNAK  (1 << 2)    /* send ACK(0) or NAK(1) */
#define ICR_TB      (1 << 3)    /* transfer byte bit */
#define ICR_MA      (1 << 4)    /* master abort */
#define ICR_SCLE    (1 << 5)    /* master clock enable */
#define ICR_IUE     (1 << 6)    /* unit enable */
#define ICR_GCD     (1 << 7)    /* general call disable */
#define ICR_ITEIE   (1 << 8)    /* enable tx interrupts */
#define ICR_IRFIE   (1 << 9)    /* enable rx interrupts */
#define ICR_BEIE    (1 << 10)    /* enable bus error ints */
#define ICR_SSDIE   (1 << 11)    /* slave STOP detected int enable */
#define ICR_ALDIE   (1 << 12)    /* enable arbitration interrupt */
#define ICR_SADIE   (1 << 13)    /* slave address detected int enable */
#define ICR_UR      (1 << 14)    /* unit reset */

#define ISR_RWM    (1 << 0)    /* read/write mode */
#define ISR_ACKNAK (1 << 1)    /* ack/nak status */
#define ISR_UB     (1 << 2)    /* unit busy */
#define ISR_IBB    (1 << 3)    /* bus busy */
#define ISR_SSD    (1 << 4)    /* slave stop detected */
#define ISR_ALD    (1 << 5)    /* arbitration loss detected */
#define ISR_ITE    (1 << 6)    /* tx buffer empty */
#define ISR_IRF    (1 << 7)    /* rx buffer full */
#define ISR_GCAD   (1 << 8)    /* general call address detected */
#define ISR_SAD    (1 << 9)    /* slave address detected */
#define ISR_BED    (1 << 10)    /* bus error no ACK/NAK */

/*
 * USB Device Controller
 */
#define UDC_RES1 __REG(0x40600004)  /* UDC Undocumented - Reserved1 */
#define UDC_RES2 __REG(0x40600008)  /* UDC Undocumented - Reserved2 */
#define UDC_RES3 __REG(0x4060000C)  /* UDC Undocumented - Reserved3 */

#define UDCCR       __REG(0x40600000)  /* UDC Control Register */
#define UDCCR_UDE   (1 << 0) /* UDC enable */
#define UDCCR_UDA   (1 << 1) /* UDC active */
#define UDCCR_RSM   (1 << 2) /* Device resume */
#define UDCCR_RESIR (1 << 3) /* Resume interrupt request */
#define UDCCR_SUSIR (1 << 4) /* Suspend interrupt request */
#define UDCCR_SRM   (1 << 5) /* Suspend/resume interrupt mask */
#define UDCCR_RSTIR (1 << 6) /* Reset interrupt request */
#define UDCCR_REM   (1 << 7) /* Reset interrupt mask */

#define UDCCS0      __REG(0x40600010)  /* UDC Endpoint 0 Control/Status Register */
#define UDCCS0_OPR  (1 << 0) /* OUT packet ready */
#define UDCCS0_IPR  (1 << 1) /* IN packet ready */
#define UDCCS0_FTF  (1 << 2) /* Flush Tx FIFO */
#define UDCCS0_DRWF (1 << 3) /* Device remote wakeup feature */
#define UDCCS0_SST  (1 << 4) /* Sent stall */
#define UDCCS0_FST  (1 << 5) /* Force stall */
#define UDCCS0_RNE  (1 << 6) /* Receive FIFO no empty */
#define UDCCS0_SA   (1 << 7) /* Setup active */

/* Bulk IN - Endpoint 1,6,11 */
#define UDCCS1   __REG(0x40600014)  /* UDC Endpoint 1 (IN) Control/Status Register */
#define UDCCS6   __REG(0x40600028)  /* UDC Endpoint 6 (IN) Control/Status Register */
#define UDCCS11  __REG(0x4060003C)  /* UDC Endpoint 11 (IN) Control/Status Register */

#define UDCCS_BI_TFS (1 << 0) /* Transmit FIFO service */
#define UDCCS_BI_TPC (1 << 1) /* Transmit packet complete */
#define UDCCS_BI_FTF (1 << 2) /* Flush Tx FIFO */
#define UDCCS_BI_TUR (1 << 3) /* Transmit FIFO underrun */
#define UDCCS_BI_SST (1 << 4) /* Sent stall */
#define UDCCS_BI_FST (1 << 5) /* Force stall */
#define UDCCS_BI_TSP (1 << 7) /* Transmit short packet */

/* Bulk OUT - Endpoint 2,7,12 */
#define UDCCS2   __REG(0x40600018)  /* UDC Endpoint 2 (OUT) Control/Status Register */
#define UDCCS7   __REG(0x4060002C)  /* UDC Endpoint 7 (OUT) Control/Status Register */
#define UDCCS12  __REG(0x40600040)  /* UDC Endpoint 12 (OUT) Control/Status Register */

#define UDCCS_BO_RFS (1 << 0) /* Receive FIFO service */
#define UDCCS_BO_RPC (1 << 1) /* Receive packet complete */
#define UDCCS_BO_DME (1 << 3) /* DMA enable */
#define UDCCS_BO_SST (1 << 4) /* Sent stall */
#define UDCCS_BO_FST (1 << 5) /* Force stall */
#define UDCCS_BO_RNE (1 << 6) /* Receive FIFO not empty */
#define UDCCS_BO_RSP (1 << 7) /* Receive short packet */

/* Isochronous IN - Endpoint 3,8,13 */
#define UDCCS3   __REG(0x4060001C)  /* UDC Endpoint 3 (IN) Control/Status Register */
#define UDCCS8   __REG(0x40600030)  /* UDC Endpoint 8 (IN) Control/Status Register */
#define UDCCS13  __REG(0x40600044)  /* UDC Endpoint 13 (IN) Control/Status Register */

#define UDCCS_II_TFS (1 << 0) /* Transmit FIFO service */
#define UDCCS_II_TPC (1 << 1) /* Transmit packet complete */
#define UDCCS_II_FTF (1 << 2) /* Flush Tx FIFO */
#define UDCCS_II_TUR (1 << 3) /* Transmit FIFO underrun */
#define UDCCS_II_TSP (1 << 7) /* Transmit short packet */

/* Isochronous OUT - Endpoint 4,9,14 */
#define UDCCS4   __REG(0x40600020)  /* UDC Endpoint 4 (OUT) Control/Status Register */
#define UDCCS9   __REG(0x40600034)  /* UDC Endpoint 9 (OUT) Control/Status Register */
#define UDCCS14  __REG(0x40600048)  /* UDC Endpoint 14 (OUT) Control/Status Register */

#define UDCCS_IO_RFS (1 << 0) /* Receive FIFO service */
#define UDCCS_IO_RPC (1 << 1) /* Receive packet complete */
#define UDCCS_IO_ROF (1 << 3) /* Receive overflow */
#define UDCCS_IO_DME (1 << 3) /* DMA enable */
#define UDCCS_IO_RNE (1 << 6) /* Receive FIFO not empty */
#define UDCCS_IO_RSP (1 << 7) /* Receive short packet */

/* Interrupt IN - Endpoint 5,10,15 */
#define UDCCS5   __REG(0x40600024)  /* UDC Endpoint 5 (Interrupt) Control/Status Register */
#define UDCCS10  __REG(0x40600038)  /* UDC Endpoint 10 (Interrupt) Control/Status Register */
#define UDCCS15  __REG(0x4060004C)  /* UDC Endpoint 15 (Interrupt) Control/Status Register */

#define UDCCS_INT_TFS (1 << 0) /* Transmit FIFO service */
#define UDCCS_INT_TPC (1 << 1) /* Transmit packet complete */
#define UDCCS_INT_FTF (1 << 2) /* Flush Tx FIFO */
#define UDCCS_INT_TUR (1 << 3) /* Transmit FIFO underrun */
#define UDCCS_INT_SST (1 << 4) /* Sent stall */
#define UDCCS_INT_FST (1 << 5) /* Force stall */
#define UDCCS_INT_TSP (1 << 7) /* Transmit short packet */

#define UFNRH  __REG(0x40600060)  /* UDC Frame Number Register High */
#define UFNRL  __REG(0x40600064)  /* UDC Frame Number Register Low */
#define UBCR2  __REG(0x40600068)  /* UDC Byte Count Reg 2 */
#define UBCR4  __REG(0x4060006c)  /* UDC Byte Count Reg 4 */
#define UBCR7  __REG(0x40600070)  /* UDC Byte Count Reg 7 */
#define UBCR9  __REG(0x40600074)  /* UDC Byte Count Reg 9 */
#define UBCR12 __REG(0x40600078)  /* UDC Byte Count Reg 12 */
#define UBCR14 __REG(0x4060007c)  /* UDC Byte Count Reg 14 */
#define UDDR0  __REG(0x40600080)  /* UDC Endpoint 0 Data Register */
#define UDDR1  __REG(0x40600100)  /* UDC Endpoint 1 Data Register */
#define UDDR2  __REG(0x40600180)  /* UDC Endpoint 2 Data Register */
#define UDDR3  __REG(0x40600200)  /* UDC Endpoint 3 Data Register */
#define UDDR4  __REG(0x40600400)  /* UDC Endpoint 4 Data Register */
#define UDDR5  __REG(0x406000A0)  /* UDC Endpoint 5 Data Register */
#define UDDR6  __REG(0x40600600)  /* UDC Endpoint 6 Data Register */
#define UDDR7  __REG(0x40600680)  /* UDC Endpoint 7 Data Register */
#define UDDR8  __REG(0x40600700)  /* UDC Endpoint 8 Data Register */
#define UDDR9  __REG(0x40600900)  /* UDC Endpoint 9 Data Register */
#define UDDR10 __REG(0x406000C0)  /* UDC Endpoint 10 Data Register */
#define UDDR11  __REG(0x40600B00)  /* UDC Endpoint 11 Data Register */
#define UDDR12 _REG(0x40600B80)  /* UDC Endpoint 12 Data Register */
#define UDDR13 __REG(0x40600C00)  /* UDC Endpoint 13 Data Register */
#define UDDR14 __REG(0x40600E00)  /* UDC Endpoint 14 Data Register */
#define UDDR15 __REG(0x406000E0)  /* UDC Endpoint 15 Data Register */

#define UICR0  __REG(0x40600050)  /* UDC Interrupt Control Register 0 */

#define UICR0_IM0 (1 << 0) /* Interrupt mask ep 0 */
#define UICR0_IM1 (1 << 1) /* Interrupt mask ep 1 */
#define UICR0_IM2 (1 << 2) /* Interrupt mask ep 2 */
#define UICR0_IM3 (1 << 3) /* Interrupt mask ep 3 */
#define UICR0_IM4 (1 << 4) /* Interrupt mask ep 4 */
#define UICR0_IM5 (1 << 5) /* Interrupt mask ep 5 */
#define UICR0_IM6 (1 << 6) /* Interrupt mask ep 6 */
#define UICR0_IM7 (1 << 7) /* Interrupt mask ep 7 */

#define UICR1  __REG(0x40600054)  /* UDC Interrupt Control Register 1 */

#define UICR1_IM8  (1 << 0) /* Interrupt mask ep 8 */
#define UICR1_IM9  (1 << 1) /* Interrupt mask ep 9 */
#define UICR1_IM10 (1 << 2) /* Interrupt mask ep 10 */
#define UICR1_IM11 (1 << 3) /* Interrupt mask ep 11 */
#define UICR1_IM12 (1 << 4) /* Interrupt mask ep 12 */
#define UICR1_IM13 (1 << 5) /* Interrupt mask ep 13 */
#define UICR1_IM14 (1 << 6) /* Interrupt mask ep 14 */
#define UICR1_IM15 (1 << 7) /* Interrupt mask ep 15 */

#define USIR0  __REG(0x40600058)  /* UDC Status Interrupt Register 0 */

#define USIR0_IR0 (1 << 0) /* Interrup request ep 0 */
#define USIR0_IR1 (1 << 1) /* Interrup request ep 1 */
#define USIR0_IR2 (1 << 2) /* Interrup request ep 2 */
#define USIR0_IR3 (1 << 3) /* Interrup request ep 3 */
#define USIR0_IR4 (1 << 4) /* Interrup request ep 4 */
#define USIR0_IR5 (1 << 5) /* Interrup request ep 5 */
#define USIR0_IR6 (1 << 6) /* Interrup request ep 6 */
#define USIR0_IR7 (1 << 7) /* Interrup request ep 7 */

#define USIR1  __REG(0x4060005C)  /* UDC Status Interrupt Register 1 */

#define USIR1_IR8  (1 << 0) /* Interrup request ep 8 */
#define USIR1_IR9  (1 << 1) /* Interrup request ep 9 */
#define USIR1_IR10 (1 << 2) /* Interrup request ep 10 */
#define USIR1_IR11 (1 << 3) /* Interrup request ep 11 */
#define USIR1_IR12 (1 << 4) /* Interrup request ep 12 */
#define USIR1_IR13 (1 << 5) /* Interrup request ep 13 */
#define USIR1_IR14 (1 << 6) /* Interrup request ep 14 */
#define USIR1_IR15 (1 << 7) /* Interrup request ep 15 */

/*
 * OS Timer & Match Registers
 */

#define OSMR0  __REG(0x40A00000)  /* */
#define OSMR1  __REG(0x40A00004)  /* */
#define OSMR2  __REG(0x40A00008)  /* */
#define OSMR3  __REG(0x40A0000C)  /* */
#define OSCR   __REG(0x40A00010)  /* OS Timer Counter Register */
#define OSSR   __REG(0x40A00014)  /* OS Timer Status Register */
#define OWER   __REG(0x40A00018)  /* OS Timer Watchdog Enable Register */
#define OIER   __REG(0x40A0001C)  /* OS Timer Interrupt Enable Register */
#define OSCR4  __REG(0x40A00040)  /* OS Timer Counter Register */
#define OSMR4  __REG(0x40A00080)  /* OS Timer Counter Register */

#define OSSR_M4         (1 << 4)
#define OSSR_M3  (1 << 3) /* Match status channel 3 */
#define OSSR_M2  (1 << 2) /* Match status channel 2 */
#define OSSR_M1  (1 << 1) /* Match status channel 1 */
#define OSSR_M0  (1 << 0) /* Match status channel 0 */

#define OWER_WME (1 << 0) /* Watchdog Match Enable */

#define OIER_E3  (1 << 3) /* Interrupt enable channel 3 */
#define OIER_E2  (1 << 2) /* Interrupt enable channel 2 */
#define OIER_E1  (1 << 1) /* Interrupt enable channel 1 */
#define OIER_E0  (1 << 0) /* Interrupt enable channel 0 */

/*
 * Interrupt Controller
 */

#define ICIP  __REG(0x40D00000)  /* Interrupt Controller IRQ Pending Register */
#define ICMR  __REG(0x40D00004)  /* Interrupt Controller Mask Register */
#define ICLR  __REG(0x40D00008)  /* Interrupt Controller Level Register */
#define ICFP  __REG(0x40D0000C)  /* Interrupt Controller FIQ Pending Register */
#define ICPR  __REG(0x40D00010)  /* Interrupt Controller Pending Register */
#define ICCR  __REG(0x40D00014)  /* Interrupt Controller Control Register */
#define ICIP2           __REG(0x40D0009C)  /* Interrupt Controller IRQ Pending Register2 */
#define ICMR2           __REG(0x40D000A0)  /* Interrupt Controller Mask Register2 */
#define ICLR2           __REG(0x40D000A4)  /* Interrupt Controller Level Register2 */
#define ICFP2           __REG(0x40D000A8)  /* Interrupt Controller FIQ Pending Register2 */
#define ICPR2           __REG(0x40D000AC)  /* Interrupt Controller Pending Register2 */

/*
 * General Purpose I/O
 */

/*
 * Power Manager
 */
#define PMCR   __REG(0x40F50000)
#define PSR    __REG(0x40F50004)
#define PSPR   __REG(0x40F50008)
#define PCFR   __REG(0x40F5000C)
#define PWER   __REG(0x40F50010)
#define PWSR   __REG(0x40F50014)
#define PECR   __REG(0x40F50018)
#define CSER   __REG(0x40F5001C)
#define DCSR   __REG(0x40F50080)
#define JCONR  __REG(0x40F50084)
#define PVCR   __REG(0x40F50100)
#define CSVCR  __REG(0x40F50104)
#define CSVCCR __REG(0x40F50108)

#define ASCR   __REG(0x40F40000)
#define ARSR   __REG(0x40F40004)
#define AD3ER  __REG(0x40F40008)
#define AD3SR  __REG(0x40F4000C)

/*
 * Core Clock
 */

#define ACCR            __REG(0x41340000)  /* Application Subsystem Clock Configuration Register */
#define ACSR            __REG(0x41340004)  /* Application Subsystem Clock Status Register */
#define AICSR           __REG(0x41340008)  /* Interrupt Control/Status Register */
#define CKENA           __REG(0x4134000C)  /* CKEN register A */
#define CKENB           __REG(0x41340010)  /* CKEN register B */
#define AC97_DIV        __REG(0x41340014)  /* AC97 clock divisor value register */
#define CKENA_4_DFC     (1 << 4)        /* NAND flash Controller Clock Enable */
#define CKENB_6_IRQ     (1 << 6) /* Interrupt Controller Clock Enable */
#define CKENA_8_DMC     (1 << 8) /* Dynamic Memory Controller Clock Enable */
#define CKENA_9_SMC     (1 << 9) /* Static Memory Controller Clock Enable */
#define CKENA_10_SRAM   (1 << 10)       /* SRAM Unit Clock Enable */
#define CKENA_21_BTUART (1 << 21) /* BTUART Unit Clock Enable */
#define CKENA_22_FFUART (1 << 22) /* FFUART Unit Clock Enable */
#define CKENA_23_STUART (1 << 22) /* STUART Unit Clock Enable */

/*
 * Static Memory controller
 */
#define MSC0  __REG(0x4A000008)
#define MSC1  __REG(0x4A00000C)

#define MEMCLKCFG __REG(0x4A000068)
#define CSADRCFG0 __REG(0x4A000080)
#define CSADRCFG1 __REG(0x4A000084)
#define CSADRCFG2 __REG(0x4A000088)
#define CSADRCFG3 __REG(0x4A00008C)

/*
 * Dynamic Memory controller
 */
#define MDCNFG   __REG(0x48100000)
#define MDREFR   __REG(0x48100004)
#define FLYCNFG  __REG(0x48100020)
#define MDMRS    __REG(0x48100040)
#define DDR_SCAL __REG(0x48100050)
#define DDR_HCAL __REG(0x48100060)
#define DDR_WCAL __REG(0x48100068)
#define EMPI     __REG(0x48100090)
#define RCOMP    __REG(0x48100100)

#define GPIO_bit(x)     (1 << ((x) & 0x1f))
#define GPLR(x)         __REG2(0x40E00000, ((x) & 0x60) >> 3)
#define GPDR(x)         __REG2(0x40E0000C, ((x) & 0x60) >> 3)
#define GPSR(x)         __REG2(0x40E00018, ((x) & 0x60) >> 3)
#define GPCR(x)         __REG2(0x40E00024, ((x) & 0x60) >> 3)
#define GRER(x)         __REG2(0x40E00030, ((x) & 0x60) >> 3)
#define GFER(x)         __REG2(0x40E0003C, ((x) & 0x60) >> 3)
#define GEDR(x)         __REG2(0x40E00048, ((x) & 0x60) >> 3)

#define APPS_PAD_BASE   0x40E10000

/* MFPR regsiter locations for each pin */

#define GPIO0_MFPR      (APPS_PAD_BASE + 0x0124)
#define GPIO1_MFPR      (APPS_PAD_BASE + 0x0128)
#define GPIO2_MFPR      (APPS_PAD_BASE + 0x412C)
#define GPIO3_MFPR      (APPS_PAD_BASE + 0x4130)
#define GPIO4_MFPR      (APPS_PAD_BASE + 0x4134)
#define GPIO5_MFPR      (APPS_PAD_BASE + 0x41C8)
#define GPIO6_MFPR      (APPS_PAD_BASE + 0x41CC)
#define GPIO7_MFPR      (APPS_PAD_BASE + 0x41D0)
#define GPIO8_MFPR      (APPS_PAD_BASE + 0x41D4)
#define GPIO9_MFPR      (APPS_PAD_BASE + 0x41D8)
#define GPIO10_MFPR     (APPS_PAD_BASE + 0x41DC)
#define GPIO11_MFPR     (APPS_PAD_BASE + 0x41E0)
#define GPIO12_MFPR     (APPS_PAD_BASE + 0x41E4)
#define GPIO13_MFPR     (APPS_PAD_BASE + 0x41E8)
#define GPIO14_MFPR     (APPS_PAD_BASE + 0x41EC)
#define GPIO15_MFPR     (APPS_PAD_BASE + 0x41F0)
#define GPIO16_MFPR     (APPS_PAD_BASE + 0x41F4)
#define GPIO17_MFPR     (APPS_PAD_BASE + 0x41F8)
#define GPIO18_MFPR     (APPS_PAD_BASE + 0x41FC)
#define GPIO19_MFPR     (APPS_PAD_BASE + 0x4200)
#define GPIO20_MFPR     (APPS_PAD_BASE + 0x4204)
#define GPIO21_MFPR     (APPS_PAD_BASE + 0x4208)
#define GPIO22_MFPR     (APPS_PAD_BASE + 0x820C)
#define GPIO23_MFPR     (APPS_PAD_BASE + 0x8210)
#define GPIO24_MFPR     (APPS_PAD_BASE + 0x8214)
#define GPIO25_MFPR     (APPS_PAD_BASE + 0x8218)
#define GPIO26_MFPR     (APPS_PAD_BASE + 0x821C)
#define GPIO27_MFPR     (APPS_PAD_BASE + 0x8220)
#define GPIO28_MFPR     (APPS_PAD_BASE + 0x8224)
#define GPIO29_MFPR     (APPS_PAD_BASE + 0x8228)
#define GPIO30_MFPR     (APPS_PAD_BASE + 0x822C)
#define GPIO31_MFPR     (APPS_PAD_BASE + 0x8230)
#define GPIO32_MFPR     (APPS_PAD_BASE + 0x8234)
#define GPIO33_MFPR     (APPS_PAD_BASE + 0x8238)
#define GPIO34_MFPR     (APPS_PAD_BASE + 0x823C)
#define GPIO35_MFPR     (APPS_PAD_BASE + 0x8240)
#define GPIO36_MFPR     (APPS_PAD_BASE + 0x8244)
#define GPIO37_MFPR     (APPS_PAD_BASE + 0x8248)
#define GPIO38_MFPR     (APPS_PAD_BASE + 0x824C)
#define GPIO39_MFPR     (APPS_PAD_BASE + 0x8250)
#define GPIO40_MFPR     (APPS_PAD_BASE + 0x8254)
#define GPIO41_MFPR     (APPS_PAD_BASE + 0x8258)
#define GPIO42_MFPR     (APPS_PAD_BASE + 0x825C)
#define GPIO43_MFPR     (APPS_PAD_BASE + 0x8260)
#define GPIO44_MFPR     (APPS_PAD_BASE + 0x8264)
#define GPIO45_MFPR     (APPS_PAD_BASE + 0x8268)
#define GPIO46_MFPR     (APPS_PAD_BASE + 0x826C)
#define GPIO47_MFPR     (APPS_PAD_BASE + 0x8270)
#define GPIO48_MFPR     (APPS_PAD_BASE + 0x8274)
#define GPIO49_MFPR     (APPS_PAD_BASE + 0x8278)
#define GPIO50_MFPR     (APPS_PAD_BASE + 0x827C)
#define GPIO51_MFPR     (APPS_PAD_BASE + 0x8280)
#define GPIO52_MFPR     (APPS_PAD_BASE + 0x8284)
#define GPIO53_MFPR     (APPS_PAD_BASE + 0x8288)
#define GPIO54_MFPR     (APPS_PAD_BASE + 0x828C)
#define GPIO55_MFPR     (APPS_PAD_BASE + 0x8290)
#define GPIO56_MFPR     (APPS_PAD_BASE + 0x8294)
#define GPIO57_MFPR     (APPS_PAD_BASE + 0x8298)
#define GPIO58_MFPR     (APPS_PAD_BASE + 0x829C)
#define GPIO59_MFPR     (APPS_PAD_BASE + 0x82A0)
#define GPIO60_MFPR     (APPS_PAD_BASE + 0x82A4)
#define GPIO61_MFPR     (APPS_PAD_BASE + 0x82A8)
#define GPIO62_MFPR     (APPS_PAD_BASE + 0x82AC)
#define GPIO63_MFPR     (APPS_PAD_BASE + 0x82D0)
#define GPIO64_MFPR     (APPS_PAD_BASE + 0x82D4)
#define GPIO65_MFPR     (APPS_PAD_BASE + 0x82D8)
#define GPIO66_MFPR     (APPS_PAD_BASE + 0x82DC)
#define GPIO67_MFPR     (APPS_PAD_BASE + 0x82E0)
#define GPIO68_MFPR     (APPS_PAD_BASE + 0x82E4)
#define GPIO69_MFPR     (APPS_PAD_BASE + 0x82E8)
#define GPIO70_MFPR     (APPS_PAD_BASE + 0x82EC)
#define GPIO71_MFPR     (APPS_PAD_BASE + 0x82F0)
#define GPIO72_MFPR     (APPS_PAD_BASE + 0x82F4)
#define GPIO73_MFPR     (APPS_PAD_BASE + 0x82F8)
#define GPIO74_MFPR     (APPS_PAD_BASE + 0x830C)
#define GPIO75_MFPR     (APPS_PAD_BASE + 0x8310)
#define GPIO76_MFPR     (APPS_PAD_BASE + 0x8314)
#define GPIO77_MFPR     (APPS_PAD_BASE + 0x8318)
#define GPIO78_MFPR     (APPS_PAD_BASE + 0x831C)
#define GPIO79_MFPR     (APPS_PAD_BASE + 0x8320)
#define GPIO80_MFPR     (APPS_PAD_BASE + 0x8324)
#define GPIO81_MFPR     (APPS_PAD_BASE + 0x8328)
#define GPIO82_MFPR     (APPS_PAD_BASE + 0x832C)
#define GPIO83_MFPR     (APPS_PAD_BASE + 0x8330)
#define GPIO84_MFPR     (APPS_PAD_BASE + 0x8334)
#define GPIO85_MFPR     (APPS_PAD_BASE + 0x8338)
#define GPIO86_MFPR     (APPS_PAD_BASE + 0x833C)
#define GPIO87_MFPR     (APPS_PAD_BASE + 0x8340)
#define GPIO88_MFPR     (APPS_PAD_BASE + 0x8344)
#define GPIO89_MFPR     (APPS_PAD_BASE + 0x8348)
#define GPIO90_MFPR     (APPS_PAD_BASE + 0x834C)
#define GPIO91_MFPR     (APPS_PAD_BASE + 0x8350)
#define GPIO92_MFPR     (APPS_PAD_BASE + 0x8354)
#define GPIO93_MFPR     (APPS_PAD_BASE + 0x8358)
#define GPIO94_MFPR     (APPS_PAD_BASE + 0x835C)
#define GPIO95_MFPR     (APPS_PAD_BASE + 0x8360)
#define GPIO96_MFPR     (APPS_PAD_BASE + 0xC364)
#define GPIO97_MFPR     (APPS_PAD_BASE + 0xC368)
#define GPIO98_MFPR     (APPS_PAD_BASE + 0xC36C)
#define GPIO99_MFPR     (APPS_PAD_BASE + 0xC370)
#define GPIO100_MFPR    (APPS_PAD_BASE + 0xC374)
#define GPIO101_MFPR    (APPS_PAD_BASE + 0xC378)
#define GPIO102_MFPR    (APPS_PAD_BASE + 0xC37C)
#define GPIO103_MFPR    (APPS_PAD_BASE + 0xC380)
#define GPIO104_MFPR    (APPS_PAD_BASE + 0xC384)
#define GPIO105_MFPR    (APPS_PAD_BASE + 0xC388)
#define GPIO106_MFPR    (APPS_PAD_BASE + 0xC38C)
#define GPIO107_MFPR    (APPS_PAD_BASE + 0xC390)
#define GPIO108_MFPR    (APPS_PAD_BASE + 0xC394)
#define GPIO109_MFPR    (APPS_PAD_BASE + 0xC398)
#define GPIO110_MFPR    (APPS_PAD_BASE + 0xC39C)
#define GPIO111_MFPR    (APPS_PAD_BASE + 0xC3A0)
#define GPIO112_MFPR    (APPS_PAD_BASE + 0xC3A4)
#define GPIO113_MFPR    (APPS_PAD_BASE + 0xC3A8)
#define GPIO114_MFPR    (APPS_PAD_BASE + 0xC3AC)
#define GPIO115_MFPR    (APPS_PAD_BASE + 0xC3B0)
#define GPIO116_MFPR    (APPS_PAD_BASE + 0xC3B4)
#define GPIO117_MFPR    (APPS_PAD_BASE + 0xC3B8)
#define GPIO118_MFPR    (APPS_PAD_BASE + 0xC3BC)
#define GPIO119_MFPR    (APPS_PAD_BASE + 0xC3C0)
#define GPIO120_MFPR    (APPS_PAD_BASE + 0xC3C4)
#define GPIO121_MFPR    (APPS_PAD_BASE + 0xC3C8)
#define GPIO122_MFPR    (APPS_PAD_BASE + 0xC3CC)
#define GPIO123_MFPR    (APPS_PAD_BASE + 0xC3D0)
#define GPIO124_MFPR    (APPS_PAD_BASE + 0xC3D4)
#define GPIO125_MFPR    (APPS_PAD_BASE + 0xC3D8)
#define GPIO126_MFPR    (APPS_PAD_BASE + 0xC3DC)
#define GPIO127_MFPR    (APPS_PAD_BASE + 0xC3E0)
#define GPIO128_MFPR    (APPS_PAD_BASE + 0xC3E4)        // MFPR for GPIO0_2
#define GPIO129_MFPR    (APPS_PAD_BASE + 0xC3E8)        // MFPR for GPIO1_2
#define GPIO130_MFPR    (APPS_PAD_BASE + 0xC3EC)        // MFPR for GPIO2_2
#define GPIO131_MFPR    (APPS_PAD_BASE + 0xC3F0)        // MFPR for GPIO3_2
#define GPIO132_MFPR    (APPS_PAD_BASE + 0xC3F4)        // MFPR for GPIO4_2
#define GPIO133_MFPR    (APPS_PAD_BASE + 0xC3F8)        // MFPR for GPIO5_2
#define GPIO134_MFPR    (APPS_PAD_BASE + 0x82B0)        // MFPR for GPIO6_2
#define GPIO135_MFPR    (APPS_PAD_BASE + 0x82B4)        // MFPR for GPIO7_2
#define GPIO136_MFPR    (APPS_PAD_BASE + 0x82B8)        // MFPR for GPIO8_2
#define GPIO137_MFPR    (APPS_PAD_BASE + 0x82BC)        // MFPR for GPIO9_2
#define GPIO138_MFPR    (APPS_PAD_BASE + 0x82C0)        // MFPR for GPIO10_2
#define GPIO139_MFPR    (APPS_PAD_BASE + 0x82C4)        // MFPR for GPIO11_2
#define GPIO140_MFPR    (APPS_PAD_BASE + 0x82C8)        // MFPR for GPIO12_2
#define GPIO141_MFPR    (APPS_PAD_BASE + 0x82CC)        // MFPR for GPIO13_2
#define GPIO142_MFPR    (APPS_PAD_BASE + 0x82FC)        // MFPR for GPIO14_2
#define GPIO143_MFPR    (APPS_PAD_BASE + 0x8300)        // MFPR for GPIO15_2
#define GPIO144_MFPR    (APPS_PAD_BASE + 0x8304)        // MFPR for GPIO16_2
#define GPIO145_MFPR    (APPS_PAD_BASE + 0x8308)        // MFPR for GPIO17_2

#define PIN_DF_ADDR0_MFPR       (APPS_PAD_BASE + 0x4178)
#define PIN_DF_ADDR1_MFPR       (APPS_PAD_BASE + 0x417C)
#define PIN_DF_ADDR2_MFPR       (APPS_PAD_BASE + 0x4180)
#define PIN_DF_ADDR3_MFPR       (APPS_PAD_BASE + 0x4184)
#define PIN_DF_CLE_MFPR         (APPS_PAD_BASE + 0x4140)
#define PIN_DF_INT_RnB_MFPR     (APPS_PAD_BASE + 0x415C)
#define PIN_DF_IO0_MFPR         (APPS_PAD_BASE + 0x4188)
#define PIN_DF_IO1_MFPR         (APPS_PAD_BASE + 0x418C)
#define PIN_DF_IO2_MFPR         (APPS_PAD_BASE + 0x4190)
#define PIN_DF_IO3_MFPR         (APPS_PAD_BASE + 0x4194)
#define PIN_DF_IO4_MFPR         (APPS_PAD_BASE + 0x4198)
#define PIN_DF_IO5_MFPR         (APPS_PAD_BASE + 0x419C)
#define PIN_DF_IO6_MFPR         (APPS_PAD_BASE + 0x41A0)
#define PIN_DF_IO7_MFPR         (APPS_PAD_BASE + 0x41A4)
#define PIN_DF_IO8_MFPR         (APPS_PAD_BASE + 0x41A8)
#define PIN_DF_IO9_MFPR         (APPS_PAD_BASE + 0x41AC)
#define PIN_DF_IO10_MFPR        (APPS_PAD_BASE + 0x41B0)
#define PIN_DF_IO11_MFPR        (APPS_PAD_BASE + 0x41B4)
#define PIN_DF_IO12_MFPR        (APPS_PAD_BASE + 0x41B8)
#define PIN_DF_IO13_MFPR        (APPS_PAD_BASE + 0x41BC)
#define PIN_DF_IO14_MFPR        (APPS_PAD_BASE + 0x41C0)
#define PIN_DF_IO15_MFPR        (APPS_PAD_BASE + 0x41C4)
#define PIN_DF_SCLK_E_MFPR      (APPS_PAD_BASE + 0x414C)
#define PIN_DF_SCLK_S_MFPR      (APPS_PAD_BASE + 0x4148)
#define PIN_DF_UNLOCK_MFPR      (APPS_PAD_BASE + 0x413C)
#define PIN_DF_nADV1_ALE_MFPR   (APPS_PAD_BASE + 0x4144)
#define PIN_DF_nADV2_ALE_MFPR   (APPS_PAD_BASE + 0x4158)
#define PIN_DF_nCS0_MFPR        (APPS_PAD_BASE + 0x4160)
#define PIN_DF_nCS1_MFPR        (APPS_PAD_BASE + 0x4164)
#define PIN_DF_nRE_nOE_MFPR     (APPS_PAD_BASE + 0x416C)
#define PIN_DF_nWE_MFPR         (APPS_PAD_BASE + 0x4168)
#define PIN_nBE0_MFPR           (APPS_PAD_BASE + 0x4150)
#define PIN_nBE1_MFPR           (APPS_PAD_BASE + 0x4154)
#define PIN_nLLA_MFPR           (APPS_PAD_BASE + 0x4174)
#define PIN_nLUA_MFPR           (APPS_PAD_BASE + 0x4170)
#define PIN_nXCVREN_MFPR        (APPS_PAD_BASE + 0x4138)

#define GPIO_IN                 0x00000000 /* Output direction */
#define GPIO_OUT                0x80000000 /* Input direction */
#define MFPR_PS                 0x40000000 /* MFPR bit 14: pull_sel */
#define MFPR_PUE                0x20000000 /* MFPR bit 13: pullup_en */
#define MFPR_PDE                0x10000000 /* MFPR bit 12: pulldown_en */
#define MFPR_DF1                0x00000000 /* MFPR bit 11-9: drive, fast 1ma */
#define MFPR_DF2                0x02000000 /* MFPR bit 11-9: drive, fast 2ma */
#define MFPR_DF3                0x04000000 /* MFPR bit 11-9: drive, fast 3ma */
#define MFPR_DF4                0x06000000 /* MFPR bit 11-9: drive, fast 4ma */
#define MFPR_DS6                0x08000000 /* MFPR bit 11-9: drive, slow 6ma */
#define MFPR_DF6                0x0a000000 /* MFPR bit 11-9: drive, fast 6ma */
#define MFPR_DS10               0x0c000000 /* MFPR bit 11-9: drive, slow 10ma */
#define MFPR_DF10               0x0e000000 /* MFPR bit 11-9: drive, fast 10ma */
#define MFPR_SS                 0x01000000 /* MFPR bit 8: sleep_sel */
#define MFPR_SD                 0x00800000 /* MFPR bit 7: sleep_data */
#define MFPR_SE                 0x00400000 /* MFPR bit 6: sleep_oe */
#define MFPR_EC                 0x00200000 /* MFPR bit 5: edge_clear */
#define MFPR_EF                 0x00100000 /* MFPR bit 4: edge_fall_en */
#define MFPR_ER                 0x00080000 /* MFPR bit 3: edge_rise_en */
#define MFPR_ALT0               0x00000000 /* MFPR bit 2-0: alternate function 0 */
#define MFPR_ALT1               0x00010000 /* MFPR bit 2-0: alternate function 1 */
#define MFPR_ALT2               0x00020000 /* MFPR bit 2-0: alternate function 2 */
#define MFPR_ALT3               0x00030000 /* MFPR bit 2-0: alternate function 3 */
#define MFPR_ALT4               0x00040000 /* MFPR bit 2-0: alternate function 4 */
#define MFPR_ALT5               0x00050000 /* MFPR bit 2-0: alternate function 5 */
#define MFPR_ALT6               0x00060000 /* MFPR bit 2-0: alternate function 6 */
#define MFPR_ALT7               0x00070000 /* MFPR bit 2-0: alternate function 7 */
#define GPIO_MD_MASK_NR         0x0000ffff
#define GPIO_MD_MASK_MFPR       0x7fff0000
#define GPIO_MD_MASK_DIR        0x80000000
#define GPIO_MD_SHIFT_NR        0
#define GPIO_MD_SHIFT_MFPR      16
#define GPIO_MD_SHIFT_DIR       31

/* Multi GPIO Modes (127 GPIOs with up to 8 alt functions) */

#define GPIO0_GPIO_MBREQ        (0|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO1_DMEM_MBGNT_R      (1|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO2_SMEM_DF_RDY       (2|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO3_SMEM_NCS_XR_2     (3|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO4_SMEM_NCS_XR_3     (4|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO5_MSHC2_SDIO_OUT    (5|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO5_MSHC2_SDIO_IN     (5|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO6_MSHC2_BS  (6|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO7_MSHC2_SCLK        (7|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO10_UTM_CLK  (10|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO11_PWM0_OUT (11|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO12_PW_OUT   (12|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO13_PWM2_OUT (13|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO14_PWM3_OUT (14|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO15_USIM_UVS0        (15|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO16_USIM_UVS1        (16|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO17_USIM_UVS2        (17|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO18_CORE_UIO_IN      (18|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO19_PM_USIM_CARD_STATUS      (19|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO20_USIM_UCLK        (20|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO21_USIM_URST        (21|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO24_CORE_SCIO_IN     (24|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO25_PM_SC_CARD_STATUS        (25|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO26_SC_UCLK  (26|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO27_SC_URST  (27|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO30_ICP_RX_DATA      (30|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO31_ICP_TX_DATA      (31|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO32_I2C_SCL_IN       (32|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO33_I2C_SDA_IN       (33|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO34_CLK_AC97_SYS     (34|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO35_AC97_SDATA_IN0   (35|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO36_AC97_SDATA_IN1   (36|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO37_AC97_SDATA_OUT   (37|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO38_AC97_SYNC_OUT    (38|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO39_CLK_AC97_BIT     (39|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO40_AC97_RESET_N_OUT (40|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO41_U2D_PHYDATAIN_0  (41|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO41_UTM_PHYDATAOUT_0 (41|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO42_U2D_PHYDATAIN_1  (42|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO42_UTM_PHYDATAOUT_1 (42|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO43_U2D_PHYDATAIN_2  (43|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO43_UTM_PHYDATAOUT_2 (43|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO44_U2D_PHYDATAIN_3  (44|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO44_UTM_PHYDATAOUT_3 (44|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO45_U2D_PHYDATAIN_4  (45|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO45_UTM_PHYDATAOUT_4 (45|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO46_U2D_PHYDATAIN_5  (46|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO46_UTM_PHYDATAOUT_5 (46|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO47_U2D_PHYDATAIN_6  (47|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO47_UTM_PHYDATAOUT_6 (47|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO48_U2D_PHYDATAIN_7  (48|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO48_UTM_PHYDATAOUT_7 (48|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO49_U2D_PHYDATAIN_0  (49|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO49_UTM_PHYDATAOUT_0 (49|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO50_U2D_PHYDATAIN_1  (50|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO50_UTM_PHYDATAOUT_1 (50|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO51_U2D_PHYDATAIN_2  (51|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO51_UTM_PHYDATAOUT_2 (51|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO52_U2D_PHYDATAIN_3  (52|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO52_UTM_PHYDATAOUT_3 (52|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO53_U2D_PHYDATAIN_4  (53|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO53_UTM_PHYDATAOUT_4 (53|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO54_U2D_PHYDATAIN_5  (54|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO54_UTM_PHYDATAOUT_5 (54|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO55_U2D_PHYDATAIN_6  (55|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO55_UTM_PHYDATAOUT_6 (55|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO56_U2D_PHYDATAIN_7  (56|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO56_UTM_PHYDATAOUT_7 (56|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO57_CI_DD_8  (57|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO58_CI_DD_9  (58|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO59_UTM_RXACTIVE     (59|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO60_U2D_RXERROR      (60|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO61_U2D_OPMODE_0     (61|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO62_U2D_OPMODE_1     (62|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO63_LCD_LDD_8_OUT    (63|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO63_LCD_LDD_8_IN     (63|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO64_LCD_LDD_9_OUT    (64|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO64_LCD_LDD_9_IN     (64|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO65_LCD_LDD_10_OUT   (65|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO65_LCD_LDD_10_IN    (65|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO66_LCD_LDD_11_OUT   (66|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO66_LCD_LDD_11_IN    (66|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO67_LCD_LDD_12_OUT   (67|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO67_LCD_LDD_12_IN    (67|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO68_LCD_LDD_13_OUT   (68|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO68_LCD_LDD_13_IN    (68|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO69_LCD_LDD_14_OUT   (69|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO69_LCD_LDD_14_IN    (69|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO70_LCD_LDD_15_OUT   (70|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO70_LCD_LDD_15_IN    (70|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO71_LCD_LDD_16_OUT   (71|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO71_LCD_LDD_16_IN    (71|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO72_LCD_LDD_17_OUT   (72|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO72_LCD_LDD_17_IN    (72|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO74_U2D_RESET        (74|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO75_MSL2_DAT_OUT_0   (75|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO75_MSL2_DAT_IN_0    (75|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO76_MSL2_DAT_OUT_1   (76|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO76_MSL2_DAT_IN_1    (76|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO77_MSL2_DAT_OUT_2   (77|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO77_MSL2_DAT_IN_2    (77|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO78_MSL2_DAT_OUT_3   (78|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO78_MSL2_DAT_IN_3    (78|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO79_MSL2_CLK_OUT     (79|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO79_MSL2_IB_CLK      (79|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO80_MSL2_STB_OUT     (80|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO80_MSL2_STB_IN      (80|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO81_MSL2_WAIT_OUT    (81|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO81_MSL2_WAIT_IN     (81|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO82_MSL2_REQ_OUT     (82|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO82_MSL2_REQ_IN      (82|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO83_SSP1_SCLK        (83|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO83_SSP1_SCLK_IN     (83|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO84_SSP1_SFRM        (84|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO84_SSP1_SFRM_IN     (84|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO85_SSP1_TXD (85|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO86_SSP1_RXD (86|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO87_SSP1_EXTCLK      (87|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO88_SSP1_SYSCLK      (88|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO89_SSP3_SCLK        (89|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO89_SSP3_SCLK_IN     (89|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO90_SSP3_SFRM        (90|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO90_SSP3_SFRM_IN     (90|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO91_SSP3_TXD (91|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO92_SSP3_RXD (92|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO93_SSP4_SCLK        (93|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO93_SSP4_SCLK_IN     (93|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO94_SSP4_SFRM        (94|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO94_SSP4_SFRM_IN     (94|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO95_SSP4_TXD (95|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO96_SSP4_RXD (96|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO97_FF_UART1_RXD     (97|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO98_FF_UART1_TXD     (98|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO99_FF_UART1_CTS     (99|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO100_FF_UART1_DCD    (100|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_SD|MFPR_ALT1)
#define GPIO101_FF_UART1_DSR    (101|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO102_FF_UART1_RI     (102|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO103_FF_UART1_DTR    (103|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO104_FF_UART1_RTS    (104|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO105_STD_UART3_CTS   (105|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO106_STD_UART3_RTS   (106|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO107_STD_UART3_TXD   (107|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO108_STD_UART3_RXD   (108|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO109_BT_UART2_RTS    (109|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO110_BT_UART2_RXD    (110|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO111_BT_UART2_TXD    (111|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO112_BT_UART2_CTS    (112|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO113_KP_MKIN_0       (113|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO114_KP_MKIN_1       (114|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO115_KP_MKIN_2       (115|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO116_KP_MKIN_3       (116|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO117_KP_MKIN_4       (117|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO118_KP_MKIN_5       (118|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO119_KP_MKIN_6       (119|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO120_KP_MKIN_7       (120|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO121_KP_MKOUT_0      (121|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO122_KP_MKOUT_1      (122|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO123_KP_MKOUT_2      (123|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO124_KP_MKOUT_3      (124|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO125_KP_MKOUT_4      (125|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO126_KP_MKOUT_5      (126|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO127_KP_MKOUT_6      (127|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)
#define GPIO133_KP_MKOUT_6      (133|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT1)

#define GPIO0_CC_DREQ   (0|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO1_DMEM_DVAL_XR      (1|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO5_MMC2_DAT_OUT_0    (5|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO5_MMC2_DAT_IN_0     (5|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO6_MMC2_DAT_OUT_1    (6|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO6_MMC2_DAT_IN_1     (6|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO7_MMC2_DAT_OUT_2    (7|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO7_MMC2_DAT_IN_2     (7|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO8_MMC2_DAT_OUT_3    (8|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO8_MMC2_DAT_IN_3     (8|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO11_EXT_SYNC_MVT_0   (11|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO12_EXT_SYNC_MVT_1   (12|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO13_OST_CHOUT_MVT_0  (13|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO14_OST_CHOUT_MVT_1  (14|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO30_STD_UART3_RXD    (30|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO31_STD_UART3_TXD    (31|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO32_AC97_SDATA_IN2   (32|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO33_AC97_SDATA_IN3   (33|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO35_SSP2_SCLK        (35|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO35_SSP2_SCLK_IN     (35|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO36_SSP2_SFRM        (36|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO36_SSP2_SFRM_IN     (36|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO37_SSP2_TXD (37|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO38_SSP2_RXD (38|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO39_SSP2_EXTCLK      (39|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO40_SSP2_SYSCLK      (40|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO41_FF_UART1_RXD     (41|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO42_FF_UART1_TXD     (42|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO43_FF_UART1_CTS     (43|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO44_FF_UART1_DCD     (44|GPIO_IN|MFPR_PDE|MFPR_DF10|MFPR_SD|MFPR_ALT2)
#define GPIO45_FF_UART1_DSR     (45|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO46_FF_UART1_RI      (46|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO47_FF_UART1_DTR     (47|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO48_FF_UART1_RTS     (48|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO49_U2D_PHYDATAIN_PF_0       (49|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO49_UTM_PHYDATAOUT_PF_0      (49|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO50_U2D_PHYDATAIN_PF_1       (50|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO50_UTM_PHYDATAOUT_PF_1      (50|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO51_U2D_PHYDATAIN_PF_2       (51|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO51_UTM_PHYDATAOUT_PF_2      (51|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO52_U2D_PHYDATAIN_PF_3       (52|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO52_UTM_PHYDATAOUT_PF_3      (52|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO53_U2D_PHYDATAIN_PF_4       (53|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO53_UTM_PHYDATAOUT_PF_4      (53|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO54_U2D_PHYDATAIN_PF_5       (54|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO54_UTM_PHYDATAOUT_PF_5      (54|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO55_U2D_PHYDATAIN_PF_6       (55|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO55_UTM_PHYDATAOUT_PF_6      (55|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO56_U2D_PHYDATAIN_PF_7       (56|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO56_UTM_PHYDATAOUT_PF_7      (56|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO58_UTM_RXVALID      (58|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO61_U2D_OPMODE_PF_0  (61|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO62_U2D_OPMODE_PF_1  (62|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO63_LCD_CS   (63|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO64_LCD_VSYNC        (64|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO69_SSP3_SCLK        (69|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO69_SSP3_SCLK_IN     (69|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO70_SSP3_SFRM        (70|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO70_SSP3_SFRM_IN     (70|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO71_SSP3_TXD (71|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO72_SSP3_RXD (72|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO73_LCD_CS   (73|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO74_LCD_VSYNC        (74|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO75_USB_P3_1_OUT     (75|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO75_USB_P3_1_IN      (75|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO76_USB_P3_2_OUT     (76|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO76_USB_P3_2_IN      (76|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO77_USB_P3_3_OUT     (77|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO77_USB_P3_3_IN      (77|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO78_USB_P3_4_OUT     (78|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO78_USB_P3_4_IN      (78|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO79_USB_P3_5_OUT     (79|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO79_USB_P3_5_IN      (79|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO80_USB_P3_6_OUT     (80|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO80_USB_P3_6_IN      (80|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO89_STD_UART3_CTS    (89|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO90_STD_UART3_RTS    (90|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO91_STD_UART3_TXD    (91|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO92_STD_UART3_RXD    (92|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO93_U2D_RESET        (93|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO94_U2D_XCVR_SELECT  (94|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO95_U2D_TERM_SELECT  (95|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO96_U2D_SUSPENDM     (96|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO97_USB_P2_2_OUT     (97|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO97_USB_P2_2_IN      (97|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO98_USB_P2_6_OUT     (98|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO98_USB_P2_6_IN      (98|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO99_USB_P2_1_OUT     (99|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO99_USB_P2_1_IN      (99|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO100_USB_P2_4_OUT    (100|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO100_USB_P2_4_IN     (100|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO101_USB_P2_8_OUT    (101|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO101_USB_P2_8_IN     (101|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO102_USB_P2_3_OUT    (102|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO102_USB_P2_3_IN     (102|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO103_USB_P2_5_OUT    (103|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO103_USB_P2_5_IN     (103|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO104_USB_P2_7_OUT    (104|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO104_USB_P2_7_IN     (104|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO105_KP_DKIN_0       (105|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO106_KP_DKIN_1       (106|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO107_KP_DKIN_2       (107|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO108_KP_DKIN_3       (108|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO109_KP_DKIN_4       (109|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO110_KP_DKIN_5       (110|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO111_KP_DKIN_6       (111|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO112_KP_DKIN_7       (112|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO113_KP_DKIN_0       (113|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO114_KP_DKIN_1       (114|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO115_KP_DKIN_2       (115|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO116_KP_DKIN_3       (116|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO117_KP_DKIN_4       (117|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO118_KP_DKIN_5       (118|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO119_KP_DKIN_6       (119|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO120_KP_DKIN_7       (120|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO121_KP_DKIN_6       (121|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO122_KP_DKIN_5       (122|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO123_KP_DKIN_4       (123|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO124_KP_DKIN_3       (124|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO125_KP_DKIN_2       (125|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO126_KP_DKIN_1       (126|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT2)
#define GPIO127_KP_DKIN_0       (127|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT2)

#define GPIO5_SMEM_DF_NPIOR     (5|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO6_SMEM_DF_NPIOW     (6|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO7_SMEM_DF_NIOIS16   (7|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO8_SMEM_DF_NPWAIT    (8|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO11_AC97_SDATA_IN2   (11|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO12_AC97_SDATA_IN3   (12|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO18_MSHC_SDIO_OUT    (18|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO18_MSHC_SDIO_IN     (18|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO19_MSHC_BS  (19|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO20_MSHC_SCLK        (20|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO24_MSHC2_SDIO_OUT   (24|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO24_MSHC2_SDIO_IN    (24|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO25_MSHC2_BS (25|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO26_MSHC2_SCLK       (26|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO30_CLK_MMC2 (30|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO31_MMC2_CMD_OUT     (31|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO31_MMC2_CMD_IN      (31|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO34_UTM_RXVALID      (34|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO35_UTM_RXACTIVE     (35|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO36_U2D_RXERROR      (36|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO37_U2D_OPMODE_0     (37|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO38_U2D_OPMODE_1     (38|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO39_U2D_TXVALID      (39|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO40_UTM_TXREADY      (40|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO41_U2D_PHYDATAIN_PF_0       (41|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO41_UTM_PHYDATAOUT_PF_0      (41|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO42_U2D_PHYDATAIN_PF_1       (42|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO42_UTM_PHYDATAOUT_PF_1      (42|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO43_U2D_PHYDATAIN_PF_2       (43|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO43_UTM_PHYDATAOUT_PF_2      (43|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO44_U2D_PHYDATAIN_PF_3       (44|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO44_UTM_PHYDATAOUT_PF_3      (44|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO45_U2D_PHYDATAIN_PF_4       (45|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO45_UTM_PHYDATAOUT_PF_4      (45|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO46_U2D_PHYDATAIN_PF_5       (46|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO46_UTM_PHYDATAOUT_PF_5      (46|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO47_U2D_PHYDATAIN_PF_6       (47|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO47_UTM_PHYDATAOUT_PF_6      (47|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO48_U2D_PHYDATAIN_PF_7       (48|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO48_UTM_PHYDATAOUT_PF_7      (48|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO65_U2D_XCVR_SELECT  (65|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO66_U2D_TERM_SELECT  (66|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO67_U2D_SUSPENDM     (67|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO68_UTM_LINESTATE_0  (68|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO69_UTM_LINESTATE_1  (69|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO70_U2D_TXVALID      (70|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO71_UTM_TXREADY      (71|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO75_U2D_PHYDATAIN_0  (75|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO75_UTM_PHYDATAOUT_0 (75|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO76_U2D_PHYDATAIN_1  (76|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO76_UTM_PHYDATAOUT_1 (76|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO77_U2D_PHYDATAIN_2  (77|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO77_UTM_PHYDATAOUT_2 (77|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO78_U2D_PHYDATAIN_3  (78|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO78_UTM_PHYDATAOUT_3 (78|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO79_U2D_PHYDATAIN_4  (79|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO79_UTM_PHYDATAOUT_4 (79|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO80_U2D_PHYDATAIN_5  (80|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO80_UTM_PHYDATAOUT_5 (80|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO81_U2D_PHYDATAIN_6  (81|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO81_UTM_PHYDATAOUT_6 (81|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO82_U2D_PHYDATAIN_7  (82|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO82_UTM_PHYDATAOUT_7 (82|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO83_KP_DKIN_0        (83|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO84_KP_DKIN_1        (84|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO85_KP_DKIN_2        (85|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO86_KP_DKIN_3        (86|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO90_UTM_LINESTATE_0  (90|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO91_UTM_LINESTATE_1  (91|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO94_U2D_XCVR_SELECT_PF       (94|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO95_U2D_TERM_SELECT_PF       (95|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO98_U2D_RESET        (98|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO99_U2D_XCVR_SELECT  (99|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO100_U2D_TERM_SELECT (100|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO101_U2D_SUSPENDM    (101|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO102_UTM_LINESTATE_0 (102|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO103_UTM_LINESTATE_1 (103|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO105_STD_UART3_RTS   (105|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO106_STD_UART3_CTS   (106|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO107_STD_UART3_RXD   (107|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO108_STD_UART3_TXD   (108|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO109_BT_UART2_CTS    (109|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO110_BT_UART2_TXD    (110|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO111_BT_UART2_RXD    (111|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT3)
#define GPIO112_BT_UART2_RTS    (112|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT3)

#define GPIO5_MMC_DAT_OUT_0     (5|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO5_MMC_DAT_IN_0      (5|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO6_MMC_DAT_OUT_1     (6|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO6_MMC_DAT_IN_1      (6|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO7_MMC_DAT_OUT_2     (7|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO7_MMC_DAT_IN_2      (7|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO8_MMC_DAT_OUT_3     (8|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO8_MMC_DAT_IN_3      (8|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO14_SR_RTC_HZ_CLOCK_TIMER_MVT        (14|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO18_MMC_DAT_OUT_0    (18|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO18_MMC_DAT_IN_0     (18|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO19_MMC_DAT_OUT_1    (19|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO19_MMC_DAT_IN_1     (19|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO20_MMC_DAT_OUT_2    (20|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO20_MMC_DAT_IN_2     (20|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO21_MMC_DAT_OUT_3    (21|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO21_MMC_DAT_IN_3     (21|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO22_CLK_MMC  (22|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO23_MMC_CMD_OUT      (23|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO23_MMC_CMD_IN       (23|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO24_MMC2_DAT_OUT_0   (24|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO24_MMC2_DAT_IN_0    (24|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO25_MMC2_DAT_OUT_1   (25|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO25_MMC2_DAT_IN_1    (25|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO26_MMC2_DAT_OUT_2   (26|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO26_MMC2_DAT_IN_2    (26|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO27_MMC2_DAT_OUT_3   (27|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO27_MMC2_DAT_IN_3    (27|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO28_CLK_MMC2 (28|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO29_MMC2_CMD_OUT     (29|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO29_MMC2_CMD_IN      (29|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO30_CLK_MMC  (30|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO31_MMC_CMD_OUT      (31|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO31_MMC_CMD_IN       (31|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO37_U2D_OPMODE_PF_0  (37|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO38_U2D_OPMODE_PF_1  (38|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO39_U2D_TXVALID_PF   (39|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO41_FF_UART1_TXD     (41|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO42_FF_UART1_RXD     (42|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO43_FF_UART1_RTS     (43|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO45_FF_UART1_DTR     (45|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO47_FF_UART1_DSR     (47|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO48_FF_UART1_CTS     (48|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO65_MSL2_DAT_OUT_0   (65|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO65_MSL2_DAT_IN_0    (65|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO66_MSL2_DAT_OUT_1   (66|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO66_MSL2_DAT_IN_1    (66|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO67_MSL2_DAT_OUT_2   (67|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO67_MSL2_DAT_IN_2    (67|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO68_MSL2_DAT_OUT_3   (68|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO68_MSL2_DAT_IN_3    (68|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO69_MSL2_CLK_OUT     (69|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO69_MSL2_IB_CLK      (69|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO70_MSL2_STB_OUT     (70|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO70_MSL2_STB_IN      (70|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO71_MSL2_WAIT_OUT    (71|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO71_MSL2_WAIT_IN     (71|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO72_MSL2_REQ_OUT     (72|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO72_MSL2_REQ_IN      (72|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO75_MMC2_DAT_OUT_0   (75|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO75_MMC2_DAT_IN_0    (75|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO76_MMC2_DAT_OUT_1   (76|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO76_MMC2_DAT_IN_1    (76|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO77_MMC2_DAT_OUT_2   (77|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO77_MMC2_DAT_IN_2    (77|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO78_MMC2_DAT_OUT_3   (78|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO78_MMC2_DAT_IN_3    (78|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO79_CLK_MMC2 (79|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO80_MMC2_CMD_OUT     (80|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO80_MMC2_CMD_IN      (80|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO83_MSL_IB_DAT_1     (83|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO84_MSL_IB_DAT_2     (84|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO85_MSL_IB_DAT_3     (85|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO86_MSL_OB_DAT_1     (86|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO87_MSL_OB_DAT_2     (87|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO88_MSL_OB_DAT_3     (88|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO89_STD_UART3_RTS    (89|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO90_STD_UART3_CTS    (90|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO91_STD_UART3_RXD    (91|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO92_STD_UART3_TXD    (92|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO97_USB_P2_6_OUT     (97|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO97_USB_P2_6_IN      (97|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO98_USB_P2_2_OUT     (98|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT4)
#define GPIO98_USB_P2_2_IN      (98|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT4)

#define GPIO6_MSHC_SDIO_OUT     (6|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT5)
#define GPIO6_MSHC_SDIO_IN      (6|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT5)
#define GPIO7_MSHC_BS   (7|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT5)
#define GPIO8_MSHC_SCLK (8|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT5)
#define GPIO14_OW_DQ_IN (14|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT5)
#define GPIO31_CIR_OUT  (31|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT5)
#define GPIO37_SSP2_RXD (37|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT5)
#define GPIO38_SSP2_TXD (38|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT5)
#define GPIO65_U2D_XCVR_SELECT_PF       (65|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT5)
#define GPIO66_U2D_TERM_SELECT_PF       (66|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT5)
#define GPIO70_U2D_TXVALID_PF   (70|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT5)
#define GPIO71_SSP3_RXD (71|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT5)
#define GPIO72_SSP3_TXD (72|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT5)
#define GPIO75_MSHC2_SDIO_OUT   (75|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT5)
#define GPIO75_MSHC2_SDIO_IN    (75|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT5)
#define GPIO76_MSHC2_BS (76|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT5)
#define GPIO77_MSHC2_SCLK       (77|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT5)
#define GPIO83_U2D_TXVALID      (83|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT5)
#define GPIO84_UTM_TXREADY      (84|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT5)
#define GPIO85_UTM_RXVALID      (85|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT5)
#define GPIO86_UTM_RXACTIVE     (86|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT5)
#define GPIO87_U2D_RXERROR      (87|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT5)
#define GPIO88_U2D_OPMODE_0     (88|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT5)
#define GPIO91_SSP3_RXD (91|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT5)
#define GPIO92_SSP3_TXD (92|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT5)
#define GPIO95_SSP4_RXD (95|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT5)
#define GPIO96_SSP4_TXD (96|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT5)
#define GPIO99_U2D_XCVR_SELECT_PF       (99|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT5)
#define GPIO100_U2D_TERM_SELECT_PF      (100|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT5)

#define GPIO5_CORE_SCIO_IN      (5|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT6)
#define GPIO6_PM_SC_CARD_STATUS (6|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT6)
#define GPIO7_SC_UCLK   (7|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT6)
#define GPIO8_SC_URST   (8|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT6)
#define GPIO30_STD_UART3_TXD    (30|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT6)
#define GPIO31_STD_UART3_RXD    (31|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT6)
#define GPIO63_SR_CW_SLEEPDATA_MVT_8    (63|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT6)
#define GPIO64_SR_CW_SLEEPDATA_MVT_9    (64|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT6)
#define GPIO65_SR_CW_SLEEPDATA_MVT_10   (65|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT6)
#define GPIO66_SR_CW_SLEEPDATA_MVT_11   (66|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT6)
#define GPIO67_SR_CW_SLEEPDATA_MVT_12   (67|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT6)
#define GPIO68_SR_CW_SLEEPDATA_MVT_13   (68|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT6)
#define GPIO69_SR_CW_SLEEPDATA_MVT_14   (69|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT6)
#define GPIO70_SR_CW_SLEEPDATA_MVT_15   (70|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT6)
#define GPIO71_SR_CW_SLEEPDATA_MVT_16   (71|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT6)
#define GPIO72_EXT_MATCH_IN_MVT (72|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT6)
#define GPIO75_MSL_OB_DAT_0     (75|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT6)
#define GPIO76_MSL_OB_CLK       (76|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT6)
#define GPIO77_MSL_OB_STB       (77|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT6)
#define GPIO78_MSL_OB_WAIT      (78|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT6)
#define GPIO79_MSL_IB_DAT_0     (79|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT6)
#define GPIO80_MSL_IB_CLK       (80|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT6)
#define GPIO81_MSL_IB_STB       (81|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT6)
#define GPIO82_MSL_IB_WAIT      (82|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT6)
#define GPIO85_SSP1_RXD (85|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT6)
#define GPIO86_SSP1_TXD (86|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT6)
#define GPIO97_FF_UART1_TXD     (97|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT6)
#define GPIO98_FF_UART1_RXD     (98|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT6)
#define GPIO99_FF_UART1_RTS     (99|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT6)
#define GPIO101_FF_UART1_DTR    (101|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT6)
#define GPIO103_FF_UART1_DSR    (103|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT6)
#define GPIO104_FF_UART1_CTS    (104|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT6)

#define GPIO22_TEST_CLK_BYPASS_XSC_PLL  (22|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT7)
#define GPIO63_MSLCD_OUT_DATA_MVT_8     (63|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT7)
#define GPIO64_MSLCD_OUT_DATA_MVT_9     (64|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT7)
#define GPIO65_MSLCD_OUT_DATA_MVT_10    (65|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT7)
#define GPIO66_MSLCD_OUT_DATA_MVT_11    (66|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT7)
#define GPIO67_MSLCD_OUT_DATA_MVT_12    (67|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT7)
#define GPIO68_MSLCD_OUT_DATA_MVT_13    (68|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT7)
#define GPIO69_MSLCD_OUT_DATA_MVT_14    (69|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT7)
#define GPIO70_MSLCD_OUT_DATA_MVT_15    (70|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT7)
#define GPIO75_U2D_PHYDATAIN_PF_0       (75|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT7)
#define GPIO75_UTM_PHYDATAOUT_PF_0      (75|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT7)
#define GPIO76_U2D_PHYDATAIN_PF_1       (76|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT7)
#define GPIO76_UTM_PHYDATAOUT_PF_1      (76|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT7)
#define GPIO77_U2D_PHYDATAIN_PF_2       (77|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT7)
#define GPIO77_UTM_PHYDATAOUT_PF_2      (77|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT7)
#define GPIO78_U2D_PHYDATAIN_PF_3       (78|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT7)
#define GPIO78_UTM_PHYDATAOUT_PF_3      (78|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT7)
#define GPIO79_U2D_PHYDATAIN_PF_4       (79|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT7)
#define GPIO79_UTM_PHYDATAOUT_PF_4      (79|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT7)
#define GPIO80_U2D_PHYDATAIN_PF_5       (80|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT7)
#define GPIO80_UTM_PHYDATAOUT_PF_5      (80|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT7)
#define GPIO81_U2D_PHYDATAIN_PF_6       (81|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT7)
#define GPIO81_UTM_PHYDATAOUT_PF_6      (81|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT7)
#define GPIO82_U2D_PHYDATAIN_PF_7       (82|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT7)
#define GPIO82_UTM_PHYDATAOUT_PF_7      (82|GPIO_IN|MFPR_PDE|MFPR_DF3|MFPR_ALT7)
#define GPIO83_U2D_TXVALID_PF   (83|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT7)
#define GPIO88_U2D_OPMODE_PF_0  (88|GPIO_OUT|MFPR_PDE|MFPR_DF3|MFPR_ALT7)

/* Data Flash Controller Registers */
#define NDCR            __REG(0x43100000)  /* Data Flash Control register */
#define NDTR0CS0        __REG(0x43100004)  /* Data Controller Timing Parameter 0 Register for ND_nCS$ */
#define NDTR0CS1        __REG(0x43100008)  /* Data Controller Timing Parameter 0 Register for ND_nCS$ */
#define NDTR1CS0        __REG(0x4310000C)  /* Data Controller Timing Parameter 1 Register for ND_nCS$ */
#define NDTR1CS1        __REG(0x43100010)  /* Data Controller Timing Parameter 1 Register for ND_nCS$ */
#define NDSR            __REG(0x43100014)  /* Data Controller Status Register */
#define NDPCR           __REG(0x43100018)  /* Data Controller Page Count Register */
#define NDBDR0          __REG(0x4310001C)  /* Data Controller Bad Block Register 0 */
#define NDBDR1          __REG(0x43100020)  /* Data Controller Bad Block Register 1 */
#define NDDB            __REG(0x43100040)  /* Data Controller Data Buffer */
#define NDCB0           __REG(0x43100048)  /* Data Controller Command Buffer0 */
#define NDCB1           __REG(0x4310004C)  /* Data Controller Command Buffer1 */
#define NDCB2           __REG(0x43100050)  /* Data Controller Command Buffer2 */

#define NDCR_SPARE_EN   (0x1<<31)
#define NDCR_ECC_EN     (0x1<<30)
#define NDCR_DMA_EN     (0x1<<29)
#define NDCR_ND_RUN     (0x1<<28)
#define NDCR_DWIDTH_C   (0x1<<27)
#define NDCR_DWIDTH_M   (0x1<<26)
#define NDCR_PAGE_SZ    (0x3<<24)
#define NDCR_NCSX       (0x1<<23)
#define NDCR_ND_MODE    (0x3<<21)
#define NDCR_NAND_MODE   0x0
#define NDCR_CLR_PG_CNT (0x1<<20)
#define NDCR_CLR_ECC    (0x1<<19)
#define NDCR_RD_ID_CNT  (0x7<<16)
#define NDCR_RA_START   (0x1<<15)
#define NDCR_PG_PER_BLK (0x1<<14)
#define NDCR_ND_ARB_EN  (0x1<<12)
#define NDSR_RDY        (0x1<<11)
#define NDSR_CS0_PAGED  (0x1<<10)
#define NDSR_CS1_PAGED  (0x1<<9)
#define NDSR_CS0_CMDD   (0x1<<8)
#define NDSR_CS1_CMDD   (0x1<<7)
#define NDSR_CS0_BBD    (0x1<<6)
#define NDSR_CS1_BBD    (0x1<<5)
#define NDSR_DBERR      (0x1<<4)
#define NDSR_SBERR      (0x1<<3)
#define NDSR_WRDREQ     (0x1<<2)
#define NDSR_RDDREQ     (0x1<<1)
#define NDSR_WRCMDREQ   (0x1)

#define NDCB0_AUTO_RS   (0x1<<25)
#define NDCB0_CSEL      (0x1<<24)
#define NDCB0_CMD_TYPE  (0x7<<21)
#define NDCB0_NC        (0x1<<20)
#define NDCB0_DBC       (0x1<<19)
#define NDCB0_ADDR_CYC  (0x7<<16)
#define NDCB0_CMD2      (0xff<<8)
#define NDCB0_CMD1      (0xff)

/* MFPR */
#define MFPR3_ADDR      0x40E10130
#define MFPR4_ADDR      0x40E10134

#define MFPR41_ADDR     0x40E10438
#define MFPR42_ADDR     0x40E1043C
#define MFPR43_ADDR     0x40E10440
#define MFPR44_ADDR     0x40E10444
#define MFPR45_ADDR     0x40E10448
#define MFPR46_ADDR     0x40E1044C
#define MFPR47_ADDR     0x40E10450
#define MFPR48_ADDR     0x40E10454

#define MFPR107_ADDR    0x40E10620
#define MFPR108_ADDR    0x40E10624
#define MFPR109_ADDR    0x40E10628
#define MFPR110_ADDR    0x40E1062C
#define MFPR111_ADDR    0x40E10630
#define MFPR112_ADDR    0x40E10634

#define  MFPR129_ADDR   0x40E10204
#define  MFPR130_ADDR   0x40E10208
#define  MFPR135_ADDR   0x40E1021C
#define  MFPR136_ADDR   0x40E10220
#define  MFPR137_ADDR   0x40E10224
#define  MFPR138_ADDR   0x40E10228
#define  MFPR139_ADDR   0x40E1022C
#define  MFPR140_ADDR   0x40E10230
#define  MFPR147_ADDR   0x40E1024C
#define  MFPR148_ADDR   0x40E10250
#define  MFPR149_ADDR   0x40E10254
#define  MFPR150_ADDR   0x40E10258
#define  MFPR151_ADDR   0x40E1025C
#define  MFPR152_ADDR   0x40E10260
#define  MFPR153_ADDR   0x40E10264
#define  MFPR154_ADDR   0x40E10268
#define  MFPR155_ADDR   0x40E1026C
#define  MFPR156_ADDR   0x40E10270
#define  MFPR157_ADDR   0x40E10274
#define  MFPR158_ADDR   0x40E10278
#define  MFPR159_ADDR   0x40E1027C
#define  MFPR160_ADDR   0x40E10280
#define  MFPR161_ADDR   0x40E10284
#define  MFPR162_ADDR   0x40E10288

#endif
